Field of the Invention
Embodiments of the invention relate to a display device and a method for driving the same.
Discussion of the Related Art
An active matrix liquid crystal display displays a motion picture using a thin film transistor (TFT) as a switching element. The active matrix liquid crystal display may be made to be smaller and more compact than a cathode ray tube (CRT) and thus may be applied to display units of portable information appliances, office equipments, computers, etc. Further, the active matrix liquid crystal display may be applied to televisions and thus is rapidly replacing the cathode ray tube.
A liquid crystal display includes a plurality of source driver integrated circuits (ICs) for supplying a data voltage to data lines of a liquid crystal display panel, a plurality of gate driver ICs for sequentially supplying a gate pulse (or a scan pulse) to gate lines of the liquid crystal display panel, a timing controller for controlling the source driver ICs and the gate driver ICs, and the like.
The timing controller supplies digital video data, clocks for sampling the digital video data, a control signal for controlling operations of the source driver ICs, etc. to the source driver ICs through an interface, for example, a mini low voltage differential signaling (LVDS) interface. The source driver ICs convert the digital video data received from the timing controller into an analog data voltage and supplies the analog data voltage to the data lines.
When the timing controller is connected to the source driver ICs in a multidrop manner through the mini LVDS interface, red (R) data transmission lines, green (G) data transmission lines, blue (B) data transmission lines, control lines for controlling operation timings of an output and a polarity conversion operation of the source driver ICs, clock transmission lines, etc., are required between the timing controller and the source driver ICs. In the mini LVDS interface, RGB data, for example, RGB digital video data and clocks are transmitted as differential signal pairs. Therefore, when odd data and even data are simultaneously transmitted, at least 14 lines for the transmission of the RGB data are required between the timing controller and the source driver ICs. When the RGB data is 10-bit data, 18 lines are required. Thus, many lines have to be formed on a source printed circuit board (PCB) mounted between the timing controller and the source driver ICs. Hence, it is difficult to reduce a width of the source PCB.
An embedded panel interface (EPI) protocol, which connects the timing controller with the source driver ICs in a point-to-point manner to minimize the number of lines between the timing controller and the source driver ICs and to stabilize the signal transmission, was disclosed in U.S. Pat. No. 8,330,699 (issued Dec. 11, 2012), U.S. Pat. No. 7,898,518 (issued Mar. 1, 2011), and U.S. Pat. No. 7,948,465 (issued May 24, 2011) which are hereby incorporated by reference in their entirety.
The EPI protocol satisfies the following interface regulations (1) to (3).
(1) A transmitting terminal of the timing controller is connected with receiving terminals of the source driver ICs via signal line pairs in the point-to-point manner.
(2) Separate clock line pairs are not connected between the timing controller and the source driver ICs. The timing controller transmits video data and control data along with a clock signal to the source driver ICs through the signal line pairs.
(3) A clock recovery circuit for clock and data recovery (CDR) function is embedded in each of the source driver ICs. The timing controller transmits a clock training pattern signal or a preamble signal to the source driver ICs, so that an output phase and an output frequency of the clock recovery circuit should be locked. The clock recovery circuit embedded in each source driver IC generates an internal clock when the clock training pattern signal and the clock signal are input through the signal line pairs.
When a phase and a frequency of the internal clock are locked, the source driver ICs feedback-input a lock signal of a high logic level indicating an output stabilization state to the timing controller. The lock signal is feedback-input to the timing controller through a lock feedback signal line connected to the timing controller and the last source driver IC.
As described above, in the EPI protocol, the timing controller transmits the clock training pattern signal to the source driver ICs before transmitting the control data and the video data of an input image to the source driver ICs. The clock recovery circuit of the source driver IC performs a clock training operation while outputting and recovering the internal clock based on the clock training pattern signal. When the phase and the frequency of the internal clock are stably locked, a data link, to which the video data of the input image is transmitted, is formed between the source driver ICs and the timing controller. The timing controller starts to transmit the video data and the control data to the source driver ICs in response to the lock signal received from the last source driver IC.
The application of the EPI technology has extended to various models. In recent, an attempt has been made to reduce the number of lines between the timing controller and the source driver ICs using a method for connecting the timing controller with the source driver ICs in the multidrop manner to transmit the data through the EPI. Because an amount of data to be transmitted increases when the timing controller is connected to with the source driver ICs in the point-to-point manner, a data transmission frequency in the EPI manner is greater than that in the point-to-point manner. However, the EPI manner easily distorts a waveform of a pair of signals (P, N) transmitted to the source driver ICs due to an external noise, impedance mismatching of a printed circuit board (PCB), a difference between lengths of the signal line pair of the timing controller and the source driver ICs, etc.
An equalizer for boosting an input signal may be embedded in the source driver IC. When the input signal of the source driver IC is boosted, a noise is amplified. Hence, a glitch waveform appears in an amplified signal. When the glitch waveform is input to the clock recovery circuit of the source driver IC, an output phase and an output frequency of the clock recovery circuit are not locked. Therefore, the clock recovery circuit is converted in a unlock state. Then, the timing controller transmits the clock training pattern signal to the source driver ICs in response to the lock signal of the unlock state. However, the signal of the source driver IC is boosted depending on an equalization (EQ) setting value, and the glitch waveform is again generated. Further, the clock training is repeated, and an input image is not reproduced on the screen. Hence, an abnormal noise is displayed on the screen. As a result, it is difficult to apply the EPI technology in a state where the timing controller is connected with the source driver ICs in the multidrop manner.